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AT2004 4 channels adpcm processor with echo cancellation and conferencing page 1 of 25 ?2001 atelic system, inc atelic systems, inc. AT2004 application note preliminary 4 channels adpcm processor with echo cancellation and conferencing version 1.0 january 29, 2001 description the AT2004 is a four full - duplex channels, adpcm processor with conferencing and echo ca ncellation capabilities. it follows the g.726 itu standard for adpcm compression for 40k, 32k, 24k and 16k bitrates with selectable m - law and a - law input/output. it conforms to itu g.165/g.168 digital adaptive echo canceller specification for line echo del ay up to 20ms. using the command serial interface, each individual half - channel can be independently configured for adpcm, conferencing and echo canceling features. features 4 full channels of itu g.726 adpcm 4 full channels of itu g.165/g.168 complia nt echo cancellation with up to 20ms echo delay fast and robust convergence for adaptive echo canceller, even in the presence of background noise nonlinear processing with adaptive suppression threshold and comfort noise generation for echo canceller per c hannel selectable m - law and a - law input/output on - chip time slot assignment available internal clock generator and frame sync. generator simple 3 - wire serial command port for chip configuration conferencing capabilities for up to 3 additional sound sources applications dect voip / vodsl wireless telephone systems wireless pbx systems default settings 4 channels of m - law pcm input on xin in time slot 0, 1, 2, 3 4 channels of the corresponding adpcm output at 32kbps on xout in time slot 0, 1, 2, 3 4 chann els of adpcm input at 32kbps on yin in time slot 0, 1, 2, 3 4 channels of corresponding pcm m - law output on yout in time slot 0, 1, 2, 3 echo cancellation enabled for four channels conferencing disabled note: to change the default settings, commands coul d be sent through the 3 - wire interface.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 2 of 25 ?2001 atelic system, inc pin description pin symbol type description 16 xin i x channel data in . sampled on the falling edge of clkp during selected time slots with msb first. 20 xout o x channel data out . updated on the risi ng edge of clkp during selected time slots with msb first. 27 yin i y channel data in . sampled on the falling edge of clka during selected time slots with msb first. 25 fsy i/o y channel frame sync . master y channel frame sync. signal followed by the fir st time slot of transmission. it can be either input or output by initial setup sequence. 24 yout o y channel data out . updated on the rising edge of clka during selected time slots with msb first. 2 rstz i reset . low active signal to force chip reset. 1 3 12 xtal1/mclk xtal2 i o crystal in & out . 14.318 mhz crystal connected * * * . 17 clkp i/o pcm clock . it can be either input created by external control circuit, or output generated by internal control circuit. 26 clka i/o adpcm clock . it can be either inp ut created by external control circuit, or output generated by internal control circuit. 18 15 11 10 sync1 sync2 sync3 sync4 o o o o sync 1 . frame sync. for 1 st codec. sync 2 . frame sync. for 2 nd codec. sync 3 . frame sync. for 3 rd codec. sync 4 . frame syn c. for 4 th codec. 4 3 tm1 tm0 i i tm1 &tm0 . tie to ground for normal operation. 7 6 a1 a0 i i a1 & a0 . address id key for 3 - wire serial port. if match, 3 - wire serial port can be enabled for configuration. 22 sdi/sdo i/o serial data in . data for configur ation on the fly by 3 - wire serial port. sampled on the rising edge of sclk with lsb first. serial data out . output data after sending read memory command by 3 - wire serial port. sampled on the rising edge of sclk with lsb first. 21 sclk i serial clock . use d to write to the 3 - wire serial port registers or output data from 3 - wire serial port registers. 23 scsz i serial port chip select . low active to enable 3 - wire serial port. 28 v dd - power . 3.3 volts. 14 19 vss1 vss2 - - ground . 0 volt. * * * for clock so urce other than 14.318mhz, please contact atelic systems.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 3 of 25 ?2001 atelic system, inc AT2004 pin assignment 28 - pin sop nc 1 28 rstz 2 27 tm0 3 26 tm1 4 25 nc 5 24 a0 6 23 a1 7 22 nc 8 21 nc 9 20 sync4 10 19 sync3 11 18 xtal2 12 17 xtal1 13 16 vss1 14 15 vdd yin ckla fsy yout scsz sdi/sdo sclk xout vss2 sync1 clkp xin sync2 AT2004 sop pin assignment 1. when there are multiple AT2004 used on the same system, a1, a0 a re used to identify the chip. 2. a1, a0 are for chip id. values are from 00 to 03. they should be connected to microcontroller i/o line or hard wired to either v cc or ground.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 4 of 25 ?2001 atelic system, inc AT2004 function block diagram 8-bit pcm adpcm signal adpcm signal lawa 8-bit pcm conferencing up to 3 sources conferencing up to 3 sources 3 law to linear adpcm encoder adpcm decoder linear to law gain gain linear to law m u x adpcm reset law to linear m u x adpcm bypass lawp lawp lawa adpcm bypass 3 m u x m u x channel bypass adpcm reset m u x adpcm reset m u x channel bypass ec reset echo canceller** ec reset m u x **please refer to the next page
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 5 of 25 ?2001 atelic system, inc echo canceller block diagram: dc remover nlp m u x adaptive filter dc remover double talk detector narrow band signal detector disabling tone detector no. 5, 6, 7 signalling tone detector dc_rmv comfort noise nlp_flag ec bypass - stepsize freeze dc_rmv tone_flag a dotted line with arrow mark indicate the control bit in the per channel control command, such as lawp, ec reset, lawa, adpcm bypass, adpcm reset, channel bypass, dc_rmv, comfort noise, nlp_flag, ec bypass, stepsize, freeze and tone_flag. plea se refer to page 10, 11 and 12 for detail information. only one full channel is shown. AT2004 has additional capability to process up to 4 full channels simultaneously. note :
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 6 of 25 ?2001 atelic system, inc power the AT2004 is powered by a 3.3 v source and draws 100 ma at full operation and < 1 ma in powerdown mode. initialization there are two different classes of resets available on the AT2004 chip. for the default reset, hold the rstz pin low for 50 ms. this reset will bring the chip to a functioning default state. in the default state, the following parameters are set: 1. pins fsy, clkp, clka default to input (chip will receive these signals from external source) 2. 4 channels of 32k m - law adpcm decode r running on channels 0 - 3 3. 4 channels of 32k m - law adpcm encoder running on channels 4 - 7 4. 4 echo canceling - pairs defined as follows: a. channel 0 as reference for channel 4 b. channel 1 as reference for channel 5 c. channel 2 as reference for channel 6 d. channel 3 as reference for channel 7 5. no conferencing is selected a second type of reset involving the use of the 3 - wire serial interface can also be used direct the pin i/o configurations of fsy, clkp, and clka during reset.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 7 of 25 ?2001 atelic system, inc chip id setup the two chip id pins a0 and a1 (pins 6,7) should also be set during chip initialization. the ?chip id? is used to differentiate between AT2004 chips in a system that uses more than one AT2004 chip. when using only one chip, it is recommended to tie a0 an d a1 to digital zero. thus, when programming the AT2004 chip, you can use the chip id = ?00? to substitute wherever you see a1, a0. the maximum number of AT2004 can be used in a system is 4, and a chip id must be assigned to each AT2004 in a system. the format of a0 and a1 should be specified according to the following table: a1 a0 description 0 0 AT2004 chip id=0 0 1 AT2004 chip id=1 1 0 AT2004 chip id=2 1 1 AT2004 chip id=3 programming the AT2004 using the serial port to input commands commands for the AT2004 are entered using the 3 - wire serial interface. the ?three wires? refer to the three pins which control the interface: sdi/sdo (serial data in/serial data out), sclk (serial clock), and scsz (serial chip select). when scsz is enabled (low), the sdi is sampled every sclk signal. sampled bits are collected into an 8 - bit register and read by the dsp. the scsz signal can be held more than 8 - bits at a time in 8 - bit multiples forming a command sequence. different command sequences form the bulk of AT2004 programming. byte 1 sdi sclk scsz generic 3-byte command sequence lsb b1 b2 b3 b4 b5 b6 b7 byte 2 byte 3 command sequence overview the AT2004 understands five different types of command sequences. 1. the pll command sequences sets the operating speed of the chip. 2. the mcu7byte command sequence set the adpcm algorithms, bit - slots, delay and ec?s reference channel number. 3. the per channel control command sequence sets the echo canceling options and other options in the chip. 4. the conferencing command sequence sets the conferencing channels.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 8 of 25 ?2001 atelic system, inc a. this command sequ ence also adjusts gain control 5. chip power - up and power - down commands. pll command sequence the pll command sequence is a 3 - byte command sequence that sets the operating speed of the AT2004 to be a multiple of the input crystal mhz. format of pll command sequence byte 1 0 1 f3 f2 f1 f0 a1 a0 byte 2 n6 n5 n4 n3 n2 n1 n0 m5 byte 3 m4 m3 m2 m1 m0 p2 p1 p0 a[1:0] refers to the chip id (please refer to section talking about chip id) n[6:0] = n, binary number used for frequency multiplier m[5:0] = m, binary number used for frequency divider p[2:0] = table specialized frequency divider (please refer to table). f[3:0] = divider for clkp & clka generator. f(clka/clkp) = f(xtal) / f[3:0] table for p, frequency multiplier p = 0 bypass, pllclk = xtalclk regardl ess of n, m. p = 1 16 p = 2 8 p = 3 4 p = 4 2 p = 5 1 p = 6 no pllclk, pllclk = 0 hz (chip disabled!) p = 7 no pllclk, pllclk = 0 hz (chip disabled!) the system clock uses n , m , and p to determine the speed of the system clock using the followin g formula: system clock = (crystal_clk * n * 4) / (m * p) by default, the chip is set to run at 86 mhz using a 14.3 mhz crystal input. mcu7byte command sequence this command sequence allows the user to specify the adpcm algorithm, i/o bit - slots, delay and ec?s reference channel number. the command sequence length is variable, and is dependent on the number of channels that are specified. the command sequence consists of a header byte, a data portion consisting of 7 bytes for every channel specified, and a footer byte. the total number of bytes in the command sequence will be 2+7n where n = number of half channels specified. the channels should be sorted by the user in increasing order of ?input begin bit?. all the yin channels should be placed in sorted order before all the xin channels. below is a sample of mcu7byte command sequence for two ?half channels?.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 9 of 25 ?2001 atelic system, inc note: the format of data fields in/out, conf_ind, adpcm_ind, ec ref. chan. #, dec, rate and delay are specified below. in/out description 0 0 input on xin, output o n xout 0 1 input on xin, output on yout 1 0 input on yin, output on xout 1 1 input on yin, output on yout default: input is on xin, output is on xout for adpcm encoding functions. input is on yin, output is on yout for adpcm decoding functions. conf _ind description 0 no resource is allocated for conferencing operation 1 allocate resource for conferencing operation default: 0, no resource is allocated for conferencing adpcm_ind description 0 no resource is allocated for adpcm operation 1 allocat e resource for adpcm operation default: 1, allocate resource for adpcm operation ?ec ref. chan. #? specifies the channel number from which the echo canceller derives its reference signal. dec description 0 adpcm (input is pcm, output is adpcm) encode channel 1 adpcm (input is adpcm, output is pcm) decode channel command byte [7:0] description 0 0 0 0 0 0 a1 a0 chip setup command header with a1, a0 chip id in/out conf_ind adpcm_ ind ec ref. chan. # channel in/out source, conferencing/adpcm indicator and ec?s reference channel #. 0 dec 0 1 1 1 rate adpcm, configuration command for channel #0 delay (ms) specify delay for ec, should be multiple of 2ms input begin bit input end bit output begin bit chan 0 data output end bit these comm ands specify the begin and ending bits of input data and output data for channel #0 in/out conf_ind adpcm_ind 0 0 0 0 channel in/out source, conferencing/adpcm indicator and ec?s reference channel #. 0 dec 0 1 1 1 rate adpcm, configuration command for channel #1 delay (ms) specify delay for ec, should be multiple of 2ms input begin bit inpu t end bit output begin bit chan 1 data output end bit these commands specify the begin and ending bits of input data and output data for channel #1 1 1 1 1 1 1 1 1 footer of chip setup.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 10 of 25 ?2001 atelic system, inc default: 1 for channel 0, 1, 2, 3; 0 for channel 4, 5, 6, 7. rate description 0 0 16k adpcm bitrate 0 1 24k adpcm bitrate 1 0 32k adpcm bitrate 1 1 40k adpcm bitrate default: 10 for 32k adpcm bit - rate by default, 8 half - channels are specified. the first 4 half - channels are configured as adpcm decode and the second 4 half - channels are configured as adpcm encode. ?delay? specifies the echo delay in unit of ms. a nonzero ?delay? mean s AT2004 will allocate system resource to this channel to perform echo cancellation. all nonzero ?delay? should be at least 8ms and be an even number. per channel control command sequence the per channel control command sequence allows the user to specif y lots of parameters for each half channel. the command sequence length is variable, and is dependent on the number of channels that are specified. the format of the command consists of a header, a begin channel number byte, and a data portion containing information of each channel. the total number of bytes in the command sequence will be 2+2n where n = number of half channels specified. below is a sample of per channel control command sequence for two half channels. note: the format of each data fields like channel bypass, stepsize2, stepsize1, comfort noise2, comfort noise1, dc_rmv, nlp_flag, freeze, ec bypass, tone_flag, ec reset, adpcm reset, adpcm bypass, lawa, lawp and idle, are specified below. channel bypass description 0 normal operation 1 totally bypass, output is same as input default: 0 when channel bypass bit is set, the output of the channel will be derived directly from the input instead of f rom normal operation?s output. note that the normal operation of the channel is still performed according to the programmed operation for each individual function in the channel. command byte [7:0] description 0 0 1 1 0 0 a1 a0 per channel control command header with a1, a0 chip id channel configuration begin to begin on first channel, set to 0 high byte channel bypass stepsize2 stepzise1 comfort noise2 comfort noise1 dc_rmv nlp_flag freeze ch0 low byte ec bypass tone_flag ec reset adpcm reset adpcm bypass lawa lawp idle configurat ion for channel 0 high byte channel bypass stepsize2 stepzise1 comfort noise2 comfort noise1 dc_rmv nlp_flag freeze ch1 low byte ec bypass t one_flag ec reset adpcm reset adpcm bypass lawa lawp idle configuration for channel 1
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 11 of 25 ?2001 atelic system, inc stepsize2/stepsize1 description 0 0 gain is +3db of normal case 0 1 norma l case (default setting) 1 0 gain is - 3db of normal case 1 1 gain is - 6 db of normal case default: 01 for normal case. stepsize control the adaptation speed of adaptive filter. default setting is the empirically chosen optimal setting. reduce the stepsi ze will make echo canceller more stable (robust), however, it will take longer time to converge. increase the stepsize will have opposite effect. comfort_noise2/comfort_noise1 description 0 0 no comfort noise generation 0 1 pseudo random noise 1 0 noi se generated by clipping 1 1 not defined default: 10 for noise generated by clipping. AT2004 supports two comfort noise generation schemes. one is by generating pseudo random noise with energy matched to the energy of background noise. the other one is b y clipping the signal to the level of background noise. the later one is chosen as default setting because it sounds subjectively better. dc_rmv description 0 disable dc remover 1 enable dc remover default: 1 nlp_flag description 0 disable nlp proc essing 1 enable nlp processing default: 1 nlp (non linear processing) is to block the small amount of residual echo which may be still audible. when nlp is enabled, user can further enable or disable comfort noise generation. when nlp is disabled, there will be no comfort noise generation. freeze description 0 normal operation 1 coefficient of adaptive filter is frozen (no adaptation) default: 0 ec bypass description 0 normal operation of echo cancellation 1 echo canceller?s output is derived direc tly from dc remover output default: 0 tone_flag description 0 disable tone detection 1 enable tone detection default: 1
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 12 of 25 ?2001 atelic system, inc ec reset description 0 normal operation without reset of echo cancellation 1 reset echo canceller internal states, the output of echo canceller is ?0? default: 1 adpcm reset description 0 normal operation without reset of adpcm 1 reset adpcm internal states default: 1 when adpcm reset bit is ?1?, adpcm encoder will output ?ff?, adpcm decoder will output ?ff? for u - law and ? d5 ? for a - law. adpcm bypass description 0 normal operation with adpcm 1 bypass adpcm default: 0 lawa description 0 adpcm side u - law 1 adpcm side a - law default: 0 lawp description 0 pcm side u - law 1 adpcm side a - law default: 0 idle descripti on 0 normal operation 1 the output is tri - state during its time slot. once this bit is cleared, it will come back to normal operation default: 0 conferencing command sequence the conferencing command sequence allows the user to specify up to three dif ferent conferencing sources for conferencing with the current channel. conferencing command sequences length is variable, and is dependent on the number of channels that are specified. the format of the conferencing command consists of a header, a begin channel number byte, and a data portion containing conferencing command reference pair information. the data portion also contains information for gain control configuration. a sample 4 ?half - channel? conferencing command is given below.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 13 of 25 ?2001 atelic system, inc command byte[7:0] description 0 0 1 0 0 0 a1 a0 conferencing header & chip id channel configuration begin to begin on first channel, set to 0 gain conf. mode chan #1 ch0 chan #2 chan #3 conferencing command for channel 0 gain conf. mode chan #1 ch1 chan #2 chan #3 confer encing command for channel 1 gain conf. mode chan #1 ch2 chan #2 chan #3 conferencing command for channel 2 gain conf. mode chan #1 ch3 chan #2 chan #3 conferencing command for channel 3 note: chan #1, chan #2 and chan #3 are channel number of conferencing resource with current channel. the format of data fields gain and conf. mode are specified below. the gain of the channel is set according to the following table: gain[1:0] description 0 0 gain = 0db 0 1 gain = +6db 1 0 gain = - 12db 1 1 gain = - 6db default: gain is set to 0db. the conf. mode of the channel is set according to the following table: conf. mode[1:0] description 0 0 disable conferencing 0 1 one channel (specified by chan #1) is used for conferencing 1 0 two channels (specified by chan #1, chan #2 ) is used for conferencing 1 1 three channels (specified by chan #1, chan #2, chan #3) is used for conferencing chip power - up power - down command the chip power - up / power - down command is a single command byte which enables and disables the AT2004 chip. power - up chip mode will: 1. stop the sample processing 2. power - up the pll to the specified multiplier frequency 3. reset algorithms on the chip. power - down chip mode will: 1. stop the sample processing. 2. switch the sys tem clock to the power down clock running approximately at 125 hz. 0 0 0 1 0 0 a1 a0 power - up chip command 0 0 0 0 1 0 a1 a0 power - down chip command note: a1, a0 refers to the chip id.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 14 of 25 ?2001 atelic system, inc reference designs and additional notes sample usage of echo can celing hybrid far end talker - 9 ~ - 35dbm erl ( - 6 ~ - 11db) rxf adc txf dac x - 12 ~ - 38dbm echo - 12 ~ - 17dbm yx y + + rh u u y near end talker combo AT2004 note: ec: echo cancellation erl: echo return loss adc: analog to digital conversion dac: digital to analog conversion ec echo cancellation configuration
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 15 of 25 ?2001 atelic system, inc using the AT2004 with other combo chips AT2004 combo 0 dx dr combo 1 combo 2 combo 3 xin(16) fsy(25) sync.1(18) yout(24) clkp(17) sync2(15) sync3(11) sync4(10) (20)xout (27)yin tm1 tm0 when there are multiple AT2004 used on the same systems, a1, a0 are used to identify the chip. a1, a0 are for chip id. values are from 00-03. they should be connected to microcontroller i/o lines or wired to either vcc or ground. note: sdi, sclk, scsz are for 3-wire commands and should be connected to microcontroller i/o pins. clka and fsy. typical application of default setting uses national single channel combo (quad combo can be used to replace the 4 single combo) clka sdi sclk scsz
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 16 of 25 ?2001 atelic system, inc conferencing diagram adpcm input signal pcm output signal samples of conferencing configurations e e=adpcm encoder pcm input signal up to 3 more input signals adpcm output signal d d d d d=adpcm decoder + +
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 17 of 25 ?2001 atelic system, inc sample command sequences: adpcm, conferencing, echo canceling, 32k, m m - law, 8 - half chan nels: for convenience, each half duplex channel is assigned a number corresponding to the internal processing order of the channels. channels 0 through channel 3 correspond with adpcm decode channels and channels 4 through channel 7 corresponds with adpc m encode channels. the following is brief description of what each half duplex channel is running: channel 0: (decode adpcm channel) conferencing: conferencing disabled. gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: channel 0 is a decode channel, thus output value is saved as a reference sample. delay (0) mcu7byte command: decode (i.e. input is adpcm sample sequence) u - law output, 32k adpcm algorithm. input time slot: @yin[0:3] (beginning bit=0, ending bit=3) o utput time slot: @yout[0:7] (beginning bit=0, ending bit=7) channel 1: (decode adpcm channel) conferencing: conferencing disabled. gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: channel 1 is a decode channel, thus out put value is saved as a reference sample. delay (0) mcu7byte command: decode u - law output, 32k adpcm algorithm. input time slot: @yin[16:19] output time slot: @yout[16:23] channel 2: (decode adpcm channel) conferencing: channel 0 + channel 1 + chan nel 4. (note that conferencing always includes its own channel, in this case ch 2). gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: channel 2 is a decode channel, thus output value is saved as a reference sample. delay (0) mcu7byte command: decode u - law output, 32k adpcm algorithm. input time slot: @yin[32:35] output time slot: @yout[32:39] channel 3: (decode adpcm channel) conferencing: channel 4 + channel 5 + channel 6 gain adjustment: no output pcm gain adj ustment (0 db gain). echo canceling: channel 3 is a decode channel, thus output value is saved as a reference sample. delay (0) mcu7byte command: decode u - law output, 32k adpcm algorithm. input time slot: @yin[48:51] output time slot: @yout[48:55]
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 18 of 25 ?2001 atelic system, inc channel 4: (encode adpcm channel) conferencing: conferencing disabled. gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: echo canceling enabled with reference sample from channel 0. delay (8ms) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorithm. input time slot: @xin[0:7] output time slot: @xout[0:3] channel 5: (encode adpcm channel) conferencing: conferencing disabled. gain adjustment: no output pcm gain adjus tment (0 db gain). echo canceling: echo canceling enabled with reference sample from channel 1. delay (8ms) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorithm. input time slot: @xin[16:23] output time slot: @xout[16:19] channel 6: (encode adpcm channel) conferencing: channel 0 + channel 1 + channel 5. gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: echo canceling enabled with reference sample from channel 2. dela y (8ms) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorithm. input time slot: @xin[32:39] output time slot: @xout[32:35] channel 7: (encode adpcm channel) conferencing: channel 4 + channel 5 + channel 0. gain adjustment: no output pcm gain adjustment (0 db gain). echo canceling: echo canceling enabled with reference sample from channel 3. delay (8ms) mcu7byte command: encode (i.e. output is adpcm sample sequence) u - law input, 32k adpcm algorith m. input time slot: @xin[48:55] output time slot: @xout[48:51] the following is command sequences of conferencing, per channel control and mcu7byte: command bytes sequence specifying conferencing. 20 // begin conferencing command. this byte is fixed . 00 // this byte is fixed (usually begin specifying at channel 0). 00 // 0 channel high byte. conferencing is disabled. 00 // 0 channel low byte 00 // 1 channel high byte 00 // 1 channel low byte
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 19 of 25 ?2001 atelic system, inc 30 // 2 channel high byte. conferenci ng with chan 0. 14 // 2 channel low byte. conferencing with chan 1 and chan 4. 34 // 3 channel high byte. conferencing with chan 4. 56 // 3 channel low byte. conferencing with chan 5 and chan 6. 00 // 4 channel high byte 00 // 4 channel low byte 00 // 5 channel high byte 00 // 5 channel low byte 30 // 6 channel high byte. conferencing with chan 0. 15 // 6 channel low byte. conferencing with chan 1 and chan 5. 34 // 7 channel high byte. conferencing with cha n 4. 50 // 7 channel low byte. conferencing with chan 5 and chan 0. command bytes specifying per channel control 30 // begin per channel control. this byte is fixed. 00 // begin at 0 channel. this byte is usually fixed (usually begin sp ecifying at 0). 36 // 0 channel high byte. 70 // 0 channel low byte. 36 // 1 channel high byte. 70 // 1 channel low byte. 36 // 2 channel high byte. 70 // 2 channel low byte. 36 // 3 channel high byte. 70 // 3 channel low byte. 36 // 4 channel high byte. 70 // 4 channel low byte. 36 // 5 channel high byte. 70 // 5 channel low byte. 36 // 6 channel high byte. 70 // 6 channel low byte. 36 // 7 channel high byte. 70 // 7 channel low byte. command bytes specifying mcu7byte definition. 00 // begin mcu7byte definition. d0 // [7]: input; [6]:output; 0==x; 1==y, channel 0, yin - yout 5e // algorithm setup, default value = 5eh for expand 00 // delay 00 // begin input slot bit, adpcm 03 // end input slot bit, adpcm 00 // begin output slot bit, pcm 07 // end output slot bit, pcm d0 // [7]: input; [6]:output; 0==x; 1==y, channel 1, yin - yout 5e // algorithm setup, default value = 5eh for expand 00 // delay 10 // begin input slot bit, adpcm 13 // end input slot bit, adpcm 10 // begin output slot bit, pcm 17 // end output slot bit, pcm f0 // [7]: input; [6]:output; 0==x; 1==y, channel 2, yin - yout
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 20 of 25 ?2001 atelic system, inc 5e // algorithm setup, default value = 5eh for expand 00 // delay 20 // begin input slot bit, adpcm 23 // end input slot bit, adpcm 20 // begin output slot bit, pcm 27 // end output slot bit, pcm d0 // [7]: input; [6]:output; 0==x; 1==y, channel 3, yin - yout 5e // algorithm setup, default value = 5eh for expand 00 // delay 30 // begin input slot bit, adpcm 33 // end input slot bit, adpcm 30 // begin output slot bit, pcm 37 // end output slot bit, pcm 10 // [7]: input; [6]:output; 0==x; 1==y, channel 4, xin - xout 1e // algo rithm setup, default value = 1eh for compress 08 // delay 00 // begin input slot bit, pcm 07 // end input slot bit, pcm 00 // begin output slot bit, adpcm 03 // end output slot bit, adpcm 11 // [7]: input; [6]:output; 0==x; 1==y, channel 5, xin - xout 1e // algorithm setup, default value = 1eh for compress 08 // delay 10 // begin input slot bit, pcm 17 // end input slot bit, pcm 10 // begin output slot bit, adpcm 13 // end output slot bit, adpcm 32 // [ 7]: input; [6]:output; 0==x; 1==y, channel 6, xin - xout 1e // algorithm setup, default value = 1eh for compress 08 // delay 20 // begin input slot bit, pcm 27 // end input slot bit, pcm 20 // begin output slot bit, adpcm 23 // en d output slot bit, adpcm 33 // [7]: input; [6]:output; 0==x; 1==y, channel 7, xin - xout 1e // algorithm setup, default value = 1eh for compress 08 // delay 30 // begin input slot bit, pcm 37 // end input slot bit, pcm 30 // begin outp ut slot bit, adpcm 33 // end output slot bit, adpcm ff // end of mcu7byte commands
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 21 of 25 ?2001 atelic system, inc electrical characteristics: (0 c to 70 c) dc electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical ma ximum units notes active supply current ivcc 40 ma 1,2 power down i vccpd < 1 ma 3 input leakage i i - 1.0 +1.0 m a output leakage i o - 1.0 +1.0 m a 4 output current (2.4v) i oh 1.2 ma output current (0.4 v) i ol 4 ma notes: 1. clkp = clka = 2.048 mhz; mclk = 10mhz. 2. outputs open; inputs swinging full supply levels; 4 channel full duplex operation. 3. power down; xtal = high; fsy, clka, clkp all 0. 4. xout and yout are 3 - stated. pcm interface (0 c to 70 c) ac electr ical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes clkp, clka period t pxy 244 3906 ns 1 clkp, clka pulse width t wxyl t wxyh 100 ns clkp, clka rise fall times t rxy t fxy 10 20 ns hold time from clkp, clka to fsy t hold 0 ns 2 setup time from fsy high to clkp, clka low t sf 50 ns 2 setup time for xin, yin to clkp, clka low t sd 50 ns 2 hold time from xin, yin to clkp, clka low t hd 50 ns 2 delay time from clkp, clka to valid xout, yout t dxyo 10 150 ns 3 notes: 1. maximum width of fsy is clkp/clka period (except for signaling frame). 2. measured at v ih = 2.0v, v il = 0.8v, and 10ns maximum rise and fall times. 3. load = 150 pf + 2lsttl loads. 4. for lsb of pc m or adpcm byte.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 22 of 25 ?2001 atelic system, inc master clock/reset (0 c to 70 c) ac electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes mclk period t pm 69.84 100 125 ns 1 mclk rise/fall times t rm , t fm 10 ns rstz pulse width t rst 1 ms note: 1. mclk = 14mhz or 10mhz. serial port (0 c to 70 c) ac electrical characteristics (v dd =3.3v+20% - 10%) parameter symbol minimum typical maximum units notes sdi to sclk set up t dc 55 ns 1 sclk period t p 1 m s 1 sclk to sdi hold t cdh 55 ns 1 sclk low time t cl 250 500 ns 1 sclk high time t ch 250 500 ns 1 sclk rise and fall time t r , t f 100 ns 1 scsz to sclk set up t cc 50 ns 1 sclk to scsz hold t cch 250 ns 1 scsz inactive time t cwh 250 ns 1 sclk setup to scsz falling t scc 50 ns 1 note: 1. measured at v ih = 2.0v, v il = 0.8v, and 10ns maximum rise and fall time.
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 23 of 25 ?2001 atelic system, inc timing diagrams master clock/reset ac timing diagram mclk rst t rst t rm t fm t pm t wmh twml sclk sclk sdi t scc t cc t ch t r t f t cch t cwh t cwh t cl t p t dc t cdh note: sclk may be either high or low when scsz is taken low. 3 wire timing diagram
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 24 of 25 ?2001 atelic system, inc pcm interface ac timing diagram clkp clka fsy fsy xin yin xout yout 3 - state t hold t rxy t fxy t pxy t wxyh t wxyl t hf t sf t hf (msb) (msb) t dxyo t sd t hd t dxyz
AT2004 4 channels adpcm processor with echo cancellation and conferencing page 25 of 25 ?2001 atelic system, inc package information d c b a e eb f 28 pin sop AT2004 package information min normal max a 2.286 2.337 2.388 b 0.305 0.406 0.508 c 0.991 1.041 1.092 d 17.856 17.907 17.958 e 7.442 7.493 7.544 eb 10.312 10.414 10.516 f 0.635 -- -- g 1.194 1.27 1.346 dimension in mm. g

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